1. Field of the Invention
This invention relates to graphics. In particular, the invention relates to graphics and video processing.
2. Description of Related Art
Graphics and video systems are now being used in various platforms that are beyond the traditional applications. There is a growing need for the integration of computer-generated graphics and real-time video images in applications ranging from personal computers (PC), video conferences, to television (TV) set-top boxes. Demands for these high performance graphics and video processing systems have created many design challenges.
In a typical high performance graphics and video systems, there may be different display systems with different display formats. These different display formats may create many incompatibility problems. One problem is the difference in the aspect ratio of the display area. For example, a computer-generated image may look fine on a computer monitor but is distorted when displayed on a TV monitor. In another example, a digital image displayed on one display resolution may look different on another display resolution.
Display on a monitor may also be flickered producing undesirable viewing effects. The flickering may be a result of high frequency update rate of the horizontal lines, or the interlacing of fields in interlaced display mode. To reduce the flickering, traditional methods employ analog techniques using delay elements and switching circuits. These methods are inflexible, unreliable, and tend to be expensive.
Therefore there is a need in the technology to provide an efficient and versatile technique for processing graphical data to correct the aspect ratio and to reduce flickering.
The present invention is a method and apparatus for correcting aspect ratio of a display by scaling a source array of pixel data in a memory by a scale factor to a destination array of pixel data. The apparatus comprises a coefficient unit, a register unit, and an arithmetic unit. The coefficient unit is coupled to a buffer to load N coefficients. The register unit is coupled to the source array to load N pixel data synchronously with the coefficient unit. The N pixel data are started at a location in the source array according to the scale factor. The arithmetic unit is coupled to the coefficient unit and the register unit to perform a filtering operation on the loaded N pixel data using the corresponding N coefficients. The arithmetic unit generates a filtered output corresponding to a scaled pixel in the destination array.